1. Field of the Invention
The present invention relates to a skew adjusting method, a skew adjusting apparatus and a test apparatus and more specifically to a skew adjusting method, a skew adjusting apparatus and a test apparatus suitable for a semiconductor device test apparatus for testing operations of semiconductor devices that output a differential signal.
2. Related Art
Semiconductor devices having high speed and small amplitude differential interface have come to appear lately. Speed of the device of the highest is as high as several Gbps. In case of such super-high speed differential signal, the differential signal causes a phase difference (hereinafter referred to as skew) when length of two transmission paths of positive and negative is different even a bit and then causes a trouble that test of the semiconductor device cannot be done correctly.
This phenomenon will be explained referring to FIGS. 11 through 13. FIG. 11 shows a semiconductor device-under test 10, a differential comparator 20 and a test fixture 30 (connecting fixture) for electrically connecting the semiconductor device-under test 10 and the differential comparator 20. While the example shown in FIG. 11 shows a case when the semiconductor device-under test 10 is outputting a pair of differential signals, the semiconductor device-under test 10 outputs a large number of pairs of differential signals in reality and each pair of differential signals is applied to the differential comparator 20 provided in the pin electronics 40 for example via the test fixture 30.
The differential signals of positive POS and negative NEG are transmitted to the pin electronics 40 via single transmission lines 31 and 32 in the test fixture 30 and the differential comparator 20 provided in the pin electronics 40 judges whether or not theoretical values of the differential signals have normal logic value L or normal logic value H.
FIG. 12 shows a configuration of the differential comparator 20. The differential comparator 20 adds the differential signals inputted through a pair of input terminals 21a and 21b at an adding circuit 22. Since the differential signal NEG is a signal that has been inverted, the adding circuit 22 adds the differential signals POS and NEG by subtracting the differential signal NEG from the differential signal POS here. Next, the adding circuit 22 applies the added result to voltage comparators 23a and 23b that detect whether or not a response output signal outputted out of the semiconductor device-under test 10 has VIL, i.e., a normal logic value L, and VIH, i.e., a normal logic value H. That is, the voltage comparators 23a and 23b compare the logic value of the added signal outputted out of the adding circuit 22 by the comparative voltages VIH and VIL and output the comparison result by latching by flip-flops 24a and 24b. When the logic value of the added signal is higher than the comparative voltage VIH, the logic L is latched in the flip-flop 24a by a strobe pulse Hstb. When the logic value of the added signal is Lower than the comparative voltage VIL, the logic L is latched in the flip-flop 24b by a strobe pulse Lstb. When the logic value of the added signal is smaller than the VIH and VIL, the differential comparator 20 latches the logic H indicating ‘failure’ in the flip-flops 24a and 24b and outputs signals F-H and FL indicating ‘failure.’
FIG. 13A shows a waveform of the added signal outputted out of the adding circuit 22 and inputted to the voltage comparators 23a and 23b when the differential signals POS and NEG outputted out of the semiconductor device-under test 10 are inputted to the differential comparator 20 in a state when their phases are uniform. The adding circuit 22 executes the operation of inverting the polarity of the negative signal NEG and adding it to the positive signal POS and generates a signal having an amplitude of double of the positive signal POS as a result.
When the positive signal POS and the negative signal NEG inputted to the differential comparator 20 are uniform so as to have the same phase, changes of potential in a process of inverting from the logic L to the logic H for example of the waveform of the added signal outputted out of the adding circuit 22 changes linearly as shown in FIG. 13A. Further, changes of potential in a case of falling from the logic H to the logic L also changes linearly although not shown specifically.
By the way, when there exists even a small difference between the line lengths of the single transmission paths 31 and 32 in the test fixture 30, it causes a skew between the differential signals POS and NEG arriving at the differential comparator 20 and when the adding circuit 22 adds the differential signals POS1 and NEB1 having the skew, its added signal causes break points b1 and b2 in the changes of potential in the inversion process as shown in FIG. 13B. The break points b1 and b2 occur due to that each added value differs in sections D1 and D2 as well as D3 and D4 shown in FIG. 13B. Accordingly, an error ΔT occurs due to the break points b1 and b2 as compared to the case when the timing of crossing with the comparative voltages VIL and VIH to be compared by the voltage comparators 23a and 23b changes linearly and due to the error ΔT, an error occurs when the inversion timing of the semiconductor device-under test 10 is measured. Then, due to the measured error of the inversion timing, a problem occurs in measuring response speed of the device that the measurement cannot be done accurately.
It is noted that because the applicant is unaware of existence of prior art documents at present time, description thereof will be omitted here.
FIG. 14 shows a conventional skew adjusting method for solving this problem. An example shown in FIG. 14 represents a method of inserting a part TB called a trombone into the signal transmission paths to adjust a skew. The trombone TB is what elongates length of the signal transmission paths by a motor (not shown) to allow adjustment of the skew by constructing analog variable delay lines by the elongation of the line length.
This adjustment method allows the skew to be adjusted to an optimum state each time when a phase difference is changed due to changes of connection within the test fixture 30 (wiring within the test fixture 30 is changed every time when types of the semiconductor device-under test 10 is changed). However, such part TB is expensive and its volume is large, so that a large capacity is required to store a large number of trombones TB. Still more, it has had a drawback that it cannot adjust quickly because it operates mechanically.
FIG. 15 also shows another method. FIG. 15 shows a case when the devices within the test fixture 30 are connected by differential lines 33 composed of twisted pair lines.
When the test fixture 30 is made by the differential lines 33 however, there arises a drawback that a phase difference or asymmetry possibly contained in the differential signals outputted out of the semiconductor device-under test 10 are averaged on the way of the transmission paths and that true waveform of the semiconductor device-under test 10 cannot be measured by the differential comparator 20. That is, although it is a feature of the differential lines 33 that the asymmetry of the waveforms is averaged on the way of the transmission path, it is preferable to be able to observe the asymmetry outputted out of the semiconductor device-under test 10 as asymmetry.
It is then necessary to construct the lines within the test fixture 30, by means of separate transmission lines in order to meet this requirement. But, it is impossible to avoid the occurrence of skew, which is caused by the difference in line length as far as these separate transmission lines are used.